6

SP8852E

1

5V

1k

−

+

144

SP8852E

7

8

9

10

11

12

13

14

15

16

17

2

3

4

5

643 42 41 40

23 24

22

21

20

19

18

25 26 27 28

39

38

37

36

35

34

33

32

31

30

29

1n

REF IN

1

5V

1

µ

10n

2·2k

100p

1

5V

1n

1n

1n

VCO

LOOP FILTER

1

30V

SP8852E

27

28

33p

100p

10MHZ

Application using

crystal reference

CONTROL

MICRO

ADDRESS

STROBE

VALUES DEPEND

ON APPLICATION

OP27

ETC

*

*

*

*

Fig. 5 Typical application diagram

DESCRIPTION

Prescaler and

AM counter The programmable divider

chain is of

A and M counter construction and therefore

contains a dual modulus front end prescaler, an

A counter

which controls the dual modulus ratio and an

M counter which

performs the bulk multi-modulus division. A programmable

divider of this construction has a division ratio of

MN1A and

a minimum integer steppable division ratio of

N(N21), where

N is the prescaler value.

Data Entry and Storage

Data is loaded from the 16-bit bus into one of the internal

buffers by applying a positive pulse to the STROBE input. The

input bus can be driven from TTL or CMOS logic levels. When

STROBE is low, the inputs are isolated and the data can be

changed without affecting the programmed state.

The data is loaded into the RF buffer when the address

input is high and into the reference buffer when low. When the

STROBE input is taken high, the

A and M and reference

counters are reset and the input data is applied to the internal

storage register. When STROBE is again taken low, the data

on the input bus is stored in the selected register and the

counters released. The STROBE input is level triggered so

that if the data is changed whilst the input is high, the final

value before STROBE goes low will be stored.

In order to prevent disturbances on the VCO control voltage

when frequency changes are made, the STROBE input disables