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PDSP16116 bảng dữ liệu(PDF) 13 Page - Mitel Networks Corporation

tên linh kiện PDSP16116
Giải thích chi tiết về linh kiện  16 X 16 Bit Complex Multiplier
PDF  17 Pages
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nhà sản xuất  MITEL [Mitel Networks Corporation]
Trang chủ  http://www.mitel.com
Logo MITEL - Mitel Networks Corporation

PDSP16116 bảng dữ liệu(HTML) 13 Page - Mitel Networks Corporation

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PDSP16116
13
ELECTRICAL CHARACTERISTICS
The Electrical Characteristics are guaranteed over the following range of operating conditions, unless otherwise stated:
VDD = 15V
±10%, GND = 0V, TAMB (Industrial) = 240°C to 185°C, TAMB (Military) = 255°C to 1125°C
Static Characteristics
Min.
Typ.
Max.
Output high voltage
Output low voltage
Input high voltage
Input high voltage
Input low voltage
Input leakage current
Input capacitance
Output leakage current
Output short circuit current
10
-
0·4
-
-
0·8
110
150
300
2·4
-
3·0
2·2
-
210
250
10
VOH
VOL
VIH
VIH
VIL
IIN
CIN
IOZ
IOS
IOH = 8mA
IOL = 28mA
CLK input only
All other inputs
GND < VIN < VDD
GND < VOUT < VDD
VDD = 15·5V
V
V
V
V
V
µA
pF
µA
mA
Units
Value
Conditions
Characteristic
Symbol
P ports setup time
WTOUT1:0 setup time
GWR4:0 setup time
SFTA1:0 setup time
SFTR2:0 setup time
CEX
or CEY setup time
CEX
or CEY hold time
X or Y ports setup time
X or Y ports hold time
WTA, WTB, SOBFP or EOPSS setup time
WTA, WTB, SOBFP or EOPSS hold time
CONX or CONY setup time
CONX or CONY hold time
AR15:13 or AI15:13 setup time
AR15:13 or AI15:13 hold time
OSEL to valid P ports
OER or OEI
high to PR or PI high to high Z
OER or OEI
low to PR or PI low to high Z
OER or OEI
low to PR or PI high Z to high
OER or OEI
high to PR or PI high Z to low
CLK frequency
CLK period
CLK high time
CLK low time
VDD current (CMOS input levels)
VDD current (TTL input levels)
Characteristic
Switching Characteristics
Symbol
tCP
tCW
tCG
tCSFTA
tCSFTR
tCES
tCEH
tDS
tDH
tWS
tWH
tCONS
tCONH
tAS
tAH
tOP
tOPHZ
tOPLZ
tOPZH
tOPZL
fCLK
tCLK
tCLKH
tCLKL
IDDC
IDDT
Max.
Min.
Max.
Min.
45
30
30
60
50
-
0
-
2
-
0
-
0
-
0
35
35
45
22
24
10
-
-
-
60
100
5
5
5
5
5
11
-
11
-
14
-
14
-
14
-
-
-
-
-
-
100
30
20
-
-
PDSP16116A
5
5
5
5
5
8
-
8
-
8
-
8
-
8
-
-
-
-
-
-
50
12
12
-
-
23
20
20
30
28
-
0
-
0
-
0
-
0
-
0
20
25
25
18
18
20
-
-
-
80
130
PDSP16116
Conditions
NOTES
1. VDD = 15·5V, outputs unloaded, clock frequency = Max.
2. The PDSP16116B is specified as the PDSP16116A except that the maximum clock frequency is guaranteed at 25MHz, with a minimum
clock period of 40ns.
Fig.
9
9
9
9
9
9
9
9
9
9
10, 11
10, 11
10, 11
10, 11
9
9
9
Max.
Min.
PDSP16116D
5
5
5
5
5
8
-
8
-
8
-
8
-
8
-
-
-
-
-
-
31·7
12
12
-
-
23
20
20
30
28
-
0
-
2
-
0
-
0
-
2
20
25
25
18
18
31·5
-
-
-
80
130
Units
30pF
30pF
30pF
30pF
30pF
30pF
See Note 1
See Note 1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
mA



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