MT8930CE datasheet(21/42 Pages) MITEL

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MT8930C

9-53

Table 9. HDLC Interrupt Mask Register (Write Add. 00100

Table 10. HDLC Interrupt Status Register (Read Add. 00100

Note 1:

All interrupts will be reset after a read to the HDLC Interrupt Status Register.

BIT

NAME

DESCRIPTION

EnDcoll

A ’1’ will enable the D-channel collision interrupt.

A ’0’ will disable it. This bit is available only in TE mode.

EnEOPD

A ’1’ will enable the received End of Packet interrupt.

A ’0’ will disable it.

EnTEOP

A ’1’ will enable the transmit End of Packet interrupt.

A ’0’ will disable it.

EnFA

A ’1’ will enable the Frame Abort interrupt.

A ’0’ will disable it.

EnTxFL

A ’1’ will enable the Transmit FIFO Low interrupt.

A ’0’ will disable it.

EnTxFun

A ’1’ will enable the Transmit FIFO Underrun interrupt.

A ’0’ will disable it.

EnRxFF

A ’1’ will enable the Receive FIFO Full interrupt.

A ’0’ will disable it.

EnRxFov

A ’1’ will enable the Receive FIFO Overﬂow interrupt.

A ’0’ will disable it.

BIT

NAME

DESCRIPTION

Dcoll(1)

A ’1’ indicates that a collision has been detected on the D-channel (i.e., received E-bit

does not match with transmitted D-bit). This bit is available only in TE mode and when the

HDLC transmitter is enabled. It always reads ’0’ in NT mode.

EOPD(1)

A ’1’indicates that an end of packet has been detected on the HDLC receiver. This can be

in the form of a ﬂag, an abort sequence or as an invalid packet.

TEOP(1)

A ’1’ indicates that the transmitter has ﬁnished sending the closing ﬂag of the last packet in

the Tx FIFO, and the internal priority level is reduced from high to low.

FA(1)

A ’1’ indicates that the receiver has detected a frame abort sequence on the received data

stream.

TxFL(1)

A ’1’ indicates that the device has only four Bytes remaining in the Tx FIFO. This bit has

signiﬁcance only when the Tx FIFO is being depleted and not when it is getting loaded.

TxFun(1)

A ’1’ indicates that the Tx FIFO is empty without being given the ’end of packet’ indication.

The HDLC will transmit an abort sequence after encountering an underrun condition.

RxFF(1)

A ’1’ indicates that the HDLC controller has accumulated at least 15 bytes in the Rx

FIFO.

RxFov(1)

A ’1’ indicates that the Rx FIFO has overﬂown (i.e., an attempt to write to a full Rx FIFO).

The HDLC will always disable the receiver once the receive overﬂow has been detected.

The receiver will be re-enabled upon detection of the next ﬂag.

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