MT8809AP datasheet(3/6 Pages) MITEL

3 / 6 page

ISO-CMOS

MT8809

3-23

Functional Description

The MT8809 is an analog switch matrix with an array

size of 8 x 8. The switch array is arranged such that

there are 8 columns by 8 rows. The columns are

referred to as the Y inputs/outputs and the rows are

the X inputs/outputs. The crosspoint analog switch

array will interconnect any X I/O with any Y I/O when

turned on and provide a high degree of isolation

when turned off. The control memory consists of a 64

bit write only RAM in which the bits are selected by

the address inputs (AY0-AY2, AX0-AX2). Data is

presented to the memory on the DATA input. Data is

asynchronously written into memory whenever both

the CS (Chip Select) and STROBE inputs are low

and are latched on the rising edge of STROBE. A

logical “1” written into a memory cell turns the

corresponding crosspoint switch on and a logical “0”

turns the crosspoint off. Only the crosspoint switches

corresponding to the addressed memory location are

altered when data is written into memory. The

remaining switches retain their previous states. Any

combination of X and Y inputs/outputs can be

interconnected by establishing appropriate

patterns

in the control memory. A logical “0” on the RESET

input

will

asynchronously

return

all

memory

locations to logical “0” turning off all crosspoint

switches regardless of whether CS is high or low.

Address Decode

The six address inputs along with the STROBE and

CS (Chip Select) are logically ANDed to form an

enable signal for the resettable transparent latches.

The DATA input is buffered and is used as the input

to all latches. To write to a location, RESET must be

high and CS must go low while the address and data

are set up. Then the STROBE input is set low and

then high causing the data to be latched.

The data

can be changed while STROBE is low, however, the

corresponding

switch

will

turn

and

off

accordance with the DATA input.

DATA must be

stable on the rising edge of STROBE in order for

correct data to be written to the latch.

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