ACE9050 datasheet(13/39 Pages) MITEL

13 / 39 page

ACE9030

Radio Interface Bus - Transmit

The output Preamble word begins with a fixed pattern

1010 and then includes the source code number (Y1, Y0) for

the Result words and the status of the Lock Detect from the

synthesiser, all as described in the section Polling A to D

Converter.

The ACE9030 only drives the bus in response to a request

for data by a Normal command as described above. To avoid

any bus contention, there is a delay from the end of a data

request to the start of the response, see figure 10. The data will

start on the fifth rising edge of CL after the rising edge of

LATCHB.

Fig.10 Radio Interface transmit bus timing

Synthesiser Bus - Receive Only

The overall format to control the synthesiser is basically the

same as for the Radio Interface. There is an option of a 32 bit

sequence for the A word. The width of the LATCHC pulse is

used to set the duration of speed-up mode when changing

channels.

Fig.11 Synthesiser bus timing

DATA3

LATCHB

PREAMBLE

RESULT1

RESULT2

7 6 5 4 3 2 1 0

1 2 3 4 5

DATA (WORD A)

DATA (WORD B)

DATA (WORD C)

DATA (WORD D)

DATA (WORD A2)

LATCHC

DURATION OF MAIN SYNTHESISER SPEED-UP MODE

DATA (DUMMY WORD)

- ONLY USED TO ALLOW

LATCHC TO REMAIN HIGH

0101

FMOD

0001

1001

7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4

3 2 1 0

2 1 0

1 0 3 2 1 0 7 6 5

4 3 2 1 0 3

2 1 0

11 10 9 8 7 6 5 4 3

2 1 0

not used

1 0

1 0 11 10 9 8 7 6 5 4 3 2 1

7 6 5 4 3 2 1 0 7

6 5 4 3 2 1 0 11 10 9 8 7

6 5 4 3 2 1 0 2 1 0

not used - any data may fill space

TEST

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