LP621024E datasheet(2/15 Pages) AMICC

2 / 15 page

LP621024E Series

128K X 8 BIT CMOS SRAM

(September, 2010, Version 1.0)

AMIC Technology, Corp.

Features

General Description

Single +5V power supply

Access times: 55/70 ns (max.)

Current:

Very low power version: Operating: 70mA (max.)

Standby:

μA (max.)

Full static operation, no clock or refreshing required

All inputs and outputs are directly TTL-compatible

Common I/O using three-state output

Output enable and two chip enable inputs for easy

application

Data retention voltage: 2V (min.)

Available

32-pin

SOP,

TSOP

and

TSSOP

(8 X 13.4mm) packages

Pb-Free package only

All Pb-free (Lead-free) products are RoHS compliant

The LP621024E is a low operating current 1,048,576-bit

static random access memory organized as 131,072 words

by 8 bits and operates on a single 5V power supply.

Inputs and three-state outputs are TTL compatible and

allow for direct interfacing with common system bus

structures.

Two chip enable inputs are provided for POWER-DOWN

and device enable and an output enable input is included

for easy interfacing.

Data retention is guaranteed at a power supply voltage as

low as 2V.

Product Family

Power Dissipation

Product Family

Operating

Temperature

VCC

Range

Speed

Data Retention

(ICCDR, Typ.)

Standby

(ISB1, Typ.)

Operating

(ICC2, Typ.)

Package Type

LP621024E

°C ~ +70°C

4.5V~5.5V

55ns / 70ns

0.5

μA

10mA

32L SOP

/TSOP/TSSOP

1. Typical values are measured at VCC = 5.0V, TA = 25

°C and not 100% tested.

2. Data retention current VCC = 2.0V.

Pin Configurations

SOP

TSOP/(TSSOP)

A16

A14

A12

I/O1

I/O2

I/O3

I/O4

GND

I/O5

I/O6

I/O7

I/O8

A10

A13

CE2

A15

VCC

A11

CE1

Pin No.

Name

Pin No.

Name

A13

CE2

A15

VCC

I/O8

A16

A14

A12

I/O1

I/O2

GND

I/O4

I/O5

I/O6

I/O7

I/O3

A11

CE1

A10

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