ASX340AT datasheet(59/75 Pages) ONSEMI

59 / 75 page

ASX340AT/D Rev. H, 8/15 EN

©Semiconductor Components Industries, LLC, 2015.

ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Modes and Timing

Figure 39:

Power Up Sequence

Notes:

1. Delay between VDD and EXTCLK depends on customer devices, i.e. Xtal, Oscillator, and so on. There

is no requirement on this from the sensor.

2. Hard reset time is the minimum time required after power rails are settled. Ten clock cycles are

required for the sensor itself, assuming all power rails are settled. In a circuit where Hard reset is

performed by the RC circuit, then the RC time must include the all power rail settle time and Xtal.

3. The time for Patch Config SPI or Host, that is, t5, depends on the patches being applied.

Table 32:

Power Up Sequence

Definition

Symbol

Minimum

Typical

Maximum

Unit

VDD_PLL to VAA/VAA_PIX

–

s

VAA/VAA_PIX to VDD_IO

–

s

VDD_IO to VDD

–

s

Hard Reset

–

s

Internal Initialization

–

VDD (1.8)

VAA_PIX

VAA (2.8)

VDD_PLL

VDD_DAC (2.8)

EXTCLK

RESET_BAR

VDD_IO (2.8)

Hard Reset

Internal

Initialization

Patch Config

SPI or Host

Streaming

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