1

3

FB

1

Linear

Regulator

2M

3.3 uH

CBST

EN

AGND

Regulator IC

CSS

Internal Passives

VOUT

CINint

SYNC

EP/

PGND

Comp

RFBB

SS/TRK

VREF

1

VIN

800 kHz

PWM

RFBT

LMZ22005

SNVS686J – MARCH 2011 – REVISED AUGUST 2015

www.ti.com

7 Detailed Description

7.1 Overview

The architecture used is an internally compensated emulated peak current mode control, based on a monolithic

synchronous SIMPLE SWITCHER core capable of supporting high load currents. The output voltage is

maintained through feedback compared with an internal 0.8-V reference. For emulated peak current-mode, the

valley current is sampled on the down-slope of the inductor current. This is used as the DC value of current to

start the next cycle.

The primary application for emulated peak current-mode is high input voltage to low output voltage operating at a

narrow duty cycle. By sampling the inductor current at the end of the switching cycle and adding an external

ramp, the minimum ON-time can be significantly reduced, without the need for blanking or filtering which is

normally required for peak current-mode control.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Synchronization Input

The PWM switching frequency can be synchronized to an external frequency source. If this feature is not used,

connect this input either directly to ground, or connect to ground through a resistor of 1.5 k

Ω or less. The allowed

synchronization frequency range is 650 kHz to 950 kHz. The typical input threshold is 1.4-V transition level.

Ideally the input clock must overdrive the threshold by a factor of 2, so direct drive from 3.3-V logic through a 1.5-

k

Ω Thevenin source resistance is recommended.

NOTE

Applying a sustained logic 1 corresponds to zero Hz PWM frequency and will cause the

module to stop switching.

7.3.2 Output Overvoltage Protection

If the voltage at FB is greater than the 0.86-V internal reference the output of the error amplifier is pulled toward

14

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