VIN

GND

Loop 1

Loop 2

LMZ14203H

VOUT

High

di/dt

LMZ14203H

SNVS692G – JANUARY 2011 – REVISED OCTOBER 2015

www.ti.com

Layout Guidelines (continued)

•

Stencil Thickness – 0.125 mm to 0.15 mm

•

Reflow - Refer to solder paste supplier recommendation and optimized per board size and density

•

Refer to AN Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) for Reflow

information.

•

Maximum number of reflows allowed is one

Figure 48. Sample Reflow Profile

Table 1. Sample Reflow Profile Table

MAX TEMP

REACHED

TIME ABOVE

REACHED

TIME ABOVE

REACHED

TIME ABOVE

REACHED

PROBE

(°C)

MAX TEMP

235°C

235°C

245°C

245°C

260°C

260°C

1

242.5

6.58

0.49

6.39

0

–

0

–

2

242.5

7.1

0.55

6.31

0

7.1

0

–

3

241

7.09

0.42

6.44

0

–

0

–

10.2 Layout Example

Figure 49. Minimize Area of Current Loops in Buck Module

22

Submit Documentation Feedback

Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: LMZ14203H