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4Mb Smart 3 Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

F45_3.p65 – Rev. 3, Pub. 12/01

©2001, Micron Technology, Inc.

4Mb

SMART 3 BOOT BLOCK FLASH MEMORY

ERASE SEQUENCE

Executing an ERASE sequence sets all bits within a

block to logic 1. The command sequence necessary to

execute an ERASE is similar to that of a WRITE. To provide

added security against accidental block erasure, two con-

secutive command cycles are required to initiate anERASE

of a block. In the first cycle, addresses are “Don’t Care,”

be erased must be issued, and ERASE CONFIRM (D0h)

must be given. If a command other than ERASE CON-

FIRM is given, the write and erase status bits (SR4 and

SR5) are set, and the device is in the status register read

mode.

After the ERASE CONFIRM (D0h) is issued, the ISM

starts the ERASE of the addressed block. Any READ op-

eration outputs the status register contents on DQ0–

pleted (SR7 = 1). When the ERASE is completed, the

device is in the status register read mode until another

command is issued. Erasing the boot block also requires

ERASE SUSPENSION

The only command that may be issued while an ERASE

is in progress is ERASE SUSPEND. This command en-

ables other commands to be executed while pausing the

ERASE in progress. When the device has reached the

erase suspend mode, the erase suspend status bit (SR6)

and ISM status bit (SR7) are set. The device may now be

given a READ ARRAY, ERASE RESUME or READ STATUS

REGISTER command. After READ ARRAY has been is-

sued, any location not within the block being erased may

be read. If ERASE RESUME is issued before SR6 has been

set, the device immediately proceeds with the ERASE in

progress.

ERROR HANDLING

(SR3), write (SR4) and erase (SR5) status bits may be

checked. If one or a combination of these three bits has

been set, an error has occurred. The ISM cannot reset

these three bits. To clear these bits, CLEAR STATUS REG-

further WRITE or ERASE operations cannot resume until

the status register is cleared. Table 4 lists the combina-

tion of errors.

Table 4

STATUS BITS

SR5

SR4

SR3

ERROR DESCRIPTION

0

0

0

No errors

001

0

1

0

WRITE error

0

1

1

1

0

0

ERASE error

1

0

1

1

1

0

Command sequencing error or WRITE/ERASE error

1

1

1

NOTE: 1. SR3-SR5 must be cleared using CLEAR STATUS REGISTER.