ML6401CS-3 datasheet(7/10 Pages) MICRO-LINEAR

7 / 10 page

ML6401

Note:

Circuit in dashed lines is an optional 1175 input

network which can be replaced with circuits in

Figure 1 or 2.

CLK

VDDO

GNDO

VDDD

VDDA

VRTS

VRT

VDDA

VIN+

GNDA

VRBS

VRB

GNDD

1175 PINOUT

+5V

HC04

CLOCK IN

CLK

C10

0.1

µF

0.1

µF

470

µF

R10

Ω

C11

0.1

µF

C12

0.1

µF

C13

10pF

0.1

µF

+12V

100

Ω

120

Ω

180

Ω

R7*

Ω

POT

Ω

500

Ω

0.1

µF

VIN

–12V

*POT R7 WILL HAVE TO BE ADJUSTED

LSB

MSB

3. CXD1175 — Connect VRBS to VRB and leave VRTS

open while driving VRT with an external voltage. This

allows similar functionality to #2 preceding, but the

bias voltage (code 0) will move when the full scale

range is changed.

ML6401 — Open pin 16, drive pin 17 externally, and

connect pin 22 to pin 23. The full scale range will be

× pin 17 volts, and the bias (code 128) will occur at

1.5 volts (internally generated from bandgap). The full

scale range of the A/D must be kept below 4 volts, but

the part is only specified for full scale range of 2 volts.

Figure 3. Replacement for 1175.

4. CXD1175 — Connect VRTS to VRT and leave VRBS

open while driving VRB with an external voltage. This

allows similar functionality to #2 preceding, but the

bias voltage (code 0) will move when the full scale

range is changed.

ML6401 — Connect pin 16 to pin 17, open pin 22 and

drive pin 23 externally. The full scale range will be 2

volts (internally generated from bandgap), and the bias

(code 128) will occur at pin 23

±2% volts.

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