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ML4877 bảng dữ liệu(PDF) 2 Page - Micro Linear Corporation |
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ML4877 bảng dữ liệu(HTML) 2 Page - Micro Linear Corporation |
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2 / 11 page ![]() ML4877 2 PIN CONFIGURATION PIN DESCRIPTION PIN NAME FUNCTION 1 LEA+ Positive input for lamp error amp 2 AZR Connection to gate of external FET for high voltage regulator. Internally a zener diode to ground. 3 SS CAP Connection of optional external soft start capacitor 4RT Oscillator timing resistor 5 VREF Voltage reference output 6 L ILIM Input to current limit amplifier 7 LEA- Negative input for lamp error amplifier 8 LEA OUT Output of lamp error amplifier. External compensation capacitor connects between this pin and LEA. 9CT Oscillator timing capacitor 10 L RTD Input to resonant threshold detector PIN NAME FUNCTION 11 B SYNC Output of MOSFET driver to gate of OUT synchronous FET catch diode. 12 HVDD Battery power input to linear regulator 13 VDD Output of linear regulator. Positive power for IC. 14 L GATE1 Output of MOSFET driver. Connection to gate of one side of inverter FET drive pair. 15 ON/OFF Logic input for chip 16 L GATE2 Output of MOSFET driver. Connection to gate of one side of inverter FET drive pair. 17 PGND Power ground 18 GND Signal ground 19 B ON Connection to primary side of gate pulse transformer 20 B OFF Output of MOSFET driver. Connection to gate of FET that disables the input power. B OFF B ON GND PGND L GATE 2 ON/OFF L GATE 1 VDD HVDD B SYNC OUT 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 LEA+ AZR SS CAP RT VREF L ILIM LEA– LEA OUT CT L RTD TOP VIEW ML4877 20-Pin SSOP (R20) |
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