ML4821 datasheet(8/12 Pages) MICRO-LINEAR

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ML4821

Micro Linear

ENABLE

VREF

–

INTERNAL

BIAS

4.4V

LOGIC

POWER

VREF

VCC

500

100

300

400

500

SINE INPUT CURRENT (µA)

200

100

200

300

400

1.0

1.5

2.5

3.5

4.5

5.5

RT = 5kΩ

VRMS = 3V

Figure 8. Under-Voltage Lockout Block Diagram.

Figure 7. Gain Modulator Linearity.

VCC = 15V

TA = –55°C

TA = 25°C

TA = 125°C

–4.0

–8.0

–12

–16

–20

–24

100

120

IREF, REFERENCE SOURCE CURRENT (mA)

010

VCC SUPPLY VOLTAGE (V)

TA = 25°C

Figure 9. Total Supply Current vs. Supply Voltage.

Figure 10. Reference Load Regulation.

UNDER VOLTAGE LOCKOUT,

OVP AND CURRENT LIMIT

On power-up the ML4821 remains in the UVLO

condition; output low and quiescent current low. The IC

becomes operational when VCC reaches 16V. When VCC

drops below 9V, the UVLO condition is imposed. During

the UVLO condition, the VREF pin is “off”, making it

usable as a “flag” for starting up a down-stream PWM

converter.

OVP, SHUTDOWN, AND IC BIAS

When the input to the OVP comparator exceeds VREF, the

output of the ML4821 is inhibited. The OVP input also

functions as a “sleep” input, putting the IC into the low

quiescent UVLO state when the OVP pin is pulled below

0.7V.

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