ML2330IS-2 datasheet(5/7 Pages) MICRO-LINEAR

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ML2330

The 4-bit address/control code configures the DAC as

shown in Table 1.

Function

No operation

Select control bits and DAC A

Select control bits and DAC B

Select control bits and both DACs

Table 1.1 Address Selection

Function

Normal

Power down DAC A

Power down DAC B

Power down entire chip

Table 1.2 Power Down Selection

DAC OPERATION

The DACs are implemented using an array of equal

current sources that are decoded linearly for the four most

significant bits to improve differential linearity and to

reduce output glitch around major carries. A voltage

difference between on-board bandgap reference voltage

and GND is converted to a reference current using an

internal resistor to set up the appropriate current level in

the DACs. The DACs output current is then converted to a

voltage output by an output buffer and a resistive network.

The matching among the on-chip resistors preserves the

gain accuracy between these conversions.

FUNCTIONAL DESCRIPTION

SERIAL INTERFACE

The ML2330 communicates with microprocessors through

a synchronous, full-duplex, 3-wire interface (figure 1A &

B). At power on, the control registers are cleared and both

DACs have high impedance outputs. Data timing shown

in Figure 1C is sent MSB-first and can be transmitted in

one 4-bit and one 8-bit packet or in one 12-bit word. If a

16-bit control word is used, the first four bits are ignored.

The serial clock (SCLK) synchronizes the data transfer. Data

is transmitted and received simultaneously. Figure 2 shows

detailed serial interface timing. Note that the clock should

be low between updates. DOUT does not go into a high

impedance state if the clock idles or CS is high.

Serial data is clocked into the data registers in MSB-first

format, with the address and configuration information

preceding the actual DAC data. Data is sampled on the

SCLK’s rising edge while CS is low. Data at DOUT is

clocked out 12.5 clock cycles later, on the SCLK’s falling

edge.

Chip Select (CS) must be low to enable the read or write

operation. If CS is high, the interface is disabled and DOUT

remains unchanged. CS must go low at least 10ns before

the first clock pulse to properly clock in the first bit. With

CS low, data is clocked into the ML2330’s internal shift

can be driven at rates up to 10MHz.

SERIAL INPUT DATA FORMAT AND

CONFIGURATION CODES

The 12-bit serial input format shown in Figure 3 comprises

two DAC address bits (A1, A0), two power down control

bits (P1, P0) and eight bits of data (D7 . . . D0).

DOUT

A1 A0 P1 D7 . . . D0

DIN

Figure 3. Serial Input Format

Figure 2. Detail Interface Timing

SCLK

DIN

DOUT

tCSS

tDS

tDH

tDO

tCSH

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