ML2008, ML2009

7

desired gain setting. The relationship between the register

0 and 1 bits and the corresponding analog gain values is

shown in Tables 1 and 2. Note that C3-C0 select the

coarse gain, F3-F0 select the fine gain, and ATTEN/

GAIN

selects either gain or attenuation.

1.3 Output Buffer

The final analog stage is the output buffer. This amplifier

has internal gain of 1 and is designed to drive 600

Ω,

100pF loads. Thus, it is suitable for driving a telephone

hybrid circuit directly without any external amplifier.

1.4 Power Supplies

GND and AGND are totally isolated inside the device to

minimize coupling from the digital section into the analog

section. Typically this is less than 100

µV. However, AGND

and GND should be tied together physically near the

device and ideally close to the common power supply

ground connection.

to the analog output is greater than –60dB at 1KHz. If

decoupling of the power supplies is still necessary in a

to AGND.

Table 1. Fine Gain Settings (C3 – C0 = 0)

Ideal Gain (dB)

F3

F2

F1

F0

ATTEN/GAIN = 1 ATTEN/GAIN = 0

0000

0.0

0.0

0001

–0.1

0.1

0010

–0.2

0.2

0011

–0.3

0.3

0100

–0.4

0.4

0101

–0.5

0.5

0110

–0.6

0.6

0111

–0.7

0.7

1000

–0.8

0.8

1001

–0.9

0.9

1010

–1.0

1.0

1011

–1.1

1.1

1100

–1.2

1.2

1101

–1.3

1.3

1110

–1.4

1.4

1111

–1.5

1.5

Table 2. Coarse Gain Settings (F3 – F0 = 0)

Ideal Gain (dB)

C3

C2

C1

C0

ATTEN/GAIN = 1 ATTEN/GAIN = 0

0000

0.0

0.0

0001

–1.5

1.5

0010

–3.0

3.0

0011

–4.5

4.5

0100

–6.0

6.0

0101

–7.5

7.5

0110

–9.0

9.0

0111

–10.5

10.5

1000

–12.0

12.0

1001

–13.5

13.5

1010

–15.0

15.0

1011

–16.5

16.5

1100

–18.0

18.0

1101

–19.5

19.5

1110

–21.0

21.0

1111

–22.5

22.5

2.0 DIGITAL INTERFACE

The architecture of the digital section is shown in the

preceding black diagram.

The structure of the data registers or latches is shown in

Figures 10 and 11 for the ML2008 and ML2009,

respectively. The registers control the attenuation/gain

setting bits and with the ML2008 the power down bit.

Tables 1 and 2 describe how the data word programs the

gain.

The difference between the ML2008 and ML2009 is in the

register structure. The ML2008 is an 8-bit data bus

version. This device has one 8-bit register and one 2-bit

register to store the 9 gain setting bits and 1 powerdown

bit. Two write operations are necessary to program the full

10 data bits from eight external data pins. The address pin

A0 controls which register is being written into. The

powerdown bit, PDN, causes the device to be placed in

powerdown. When PDN = 1, the device is powered

down. In this state, the power consumption is reduced by

removing power from the analog section and forcing the

device is in powerdown, the digital section is still

functional and the current data word remains stored in the

registers. When PDN = 0, device is in normal operation.

The ML2009 is a 9-bit data bus version. This device has

one 9-bit register to store the 9 gain setting bits. The full 9

data bits can be programmed with one write operation

from nine external data pins.

The internal registers or latches are edge triggered. The

data is transferred from the external pins to the register

output on the rising edge of

WR. The address pin, A0,

controls which register the data will be written into as

shown in Figures 1 and 2. The

CS control signal selects

the device by allowing the

WR signal to latch in the data

only when

CS is low. When CS is high, WR is inhibited

from latching in new data into the registers.