TPS54341_15 datasheet(39/48 Pages) TI

39 / 48 page

BOOT

VIN

RT/CLK

GND

COMP

Input

Bypass

Capacitor

UVLO

Adjust

Resistors

Frequency

Set Resistor

Compensation

Network

Resistor

Divider

Output

Inductor

Output

Capacitor

OUT

Topside

Ground

Area

Catch

Diode

Route Boot Capacitor

Trace on another layer to

provide wide path for

topside ground

Thermal VIA

Signal VIA

SS/TR

PWRGD

Soft-Start

Capacitor

TPS54341

www.ti.com

SLVSC61 – NOVEMBER 2013

Layout

Layout is a critical portion of good power supply design. There are several signal paths that conduct fast

changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise

or degrade performance. To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR

ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by

the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 66 for a PCB layout

example. The GND pin should be tied directly to the power pad under the IC and the power pad.

The power pad should be connected to internal PCB ground planes using multiple vias directly under the IC. The

SW pin should be routed to the cathode of the catch diode and to the output inductor. Because the SW

connection is the switching node, the catch diode and output inductor should be located close to the SW pins,

and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated

load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise

so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The

additional external components can be placed approximately as shown. It may be possible to obtain acceptable

performance with alternate PCB layouts, however this layout has been shown to produce good results and is

meant as a guideline.

Figure 66. PCB Layout Example

Estimated Circuit Area

Boxing in the components in the design of Figure 46 the estimated printed circuit board area is 1.025 in2 (661

mm2). This area does not include test points or connectors.

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