LM5000 datasheet(14/24 Pages) TI

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m1 #

VINRDSON

(in V/s)

n = 1+

2mc

(no unit)

Leff =

(D')

(in rad/s)

2fs

nD'

ADC(DB) = 20log10

{[(ZcLeff)// RL]//RL} (in dB)

RFB1 + RFB2

RFB2

(

)

gmROD'

RDSON

fPC2 =

2SCC2(RC //RO)

(in Hz)

LM5000

SNVS176D – MAY 2004 – REVISED MARCH 2007

www.ti.com

Now RC can be chosen with the selected value for CC. Check to make sure that the pole fPC is still in the 10Hz to

100Hz range, change each value slightly if needed to ensure both component values are in the recommended

range. After checking the design at the end of this section, these values can be changed a little more to optimize

performance if desired. This is best done in the lab on a bench, checking the load step response with different

values until the ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should

produce a stable, high performance circuit. For improved transient response, higher values of RC (within the

range of values) should be chosen. This will improve the overall bandwidth which makes the regulator respond

more quickly to transients. If more detail is required, or the most optimal performance is desired, refer to a more

in depth discussion of compensating current mode DC/DC switching regulators.

HIGH OUTPUT CAPACITOR ESR COMPENSATION

When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control

loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding

another capacitor, CC2, directly from the compensation pin VC to ground, in parallel with the series combination of

RC and CC. The pole should be placed at the same frequency as fZ1, the ESR zero. The equation for this pole

follows:

(13)

To ensure this equation is valid, and that CC2 can be used without negatively impacting the effects of RC and CC,

fPC2 must be greater than 10fPC.

CHECKING THE DESIGN

The final step is to check the design. This is to ensure a bandwidth of ½ or less of the frequency of the RHP

zero. This is done by calculating the open-loop DC gain, ADC. After this value is known, you can calculate the

crossover visually by placing a

−20dB/decade slope at each pole, and a +20dB/decade slope for each zero. The

point at which the gain plot crosses unity gain, or 0dB, is the crossover frequency. If the crossover frequency is

at less than ½ the RHP zero, the phase margin should be high enough for stability. The phase margin can also

be improved some by adding CC2 as discussed earlier in the section. The equation for ADC is given below with

additional equations required for the calculation:

(14)

(15)

(16)

(17)

≊ 0.072fs (in A/s)

(18)

where

•

RL is the minimum load resistance

•

VIN is the maximum input voltage

•

RDSON is the value chosen from the graph "RDSON vs. VIN " in the Typical Performance Characteristics

section

(19)

SWITCH VOLTAGE LIMITS

In a flyback regulator, the maximum steady-state voltage appearing at the switch, when it is off, is set by the

transformer turns ratio, N, the output voltage, VOUT, and the maximum input voltage, VIN (Max):

VSW(OFF) = VIN (Max) + (VOUT +VF)/N

where

•

VF is the forward biased voltage of the output diode, and is typically 0.5V for Schottky diodes and 0.8V for

ultra-fast recovery diodes

(20)

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