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4

1.9

≤ V

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Start Setup Time

0.6

—

—

µs

Stop Setup Time

0.6

—

—

µs

Bus Free Time

Between Stop and Start

1.3

—

—

µs

SDA Setup Time

100

—

—

ns

SDA Hold Time

100

—

—

ns

SDA Valid Time

From SCL low to data valid

—

—

0.9

µs

SDA Acknowledge Valid Time

From SCL low to data valid

—

—

0.9

µs

50

—

—

ns

Notes:

2. Depending on the conversion command, the TH06 may hold the master during the conversion (clock stretch). At

above 100 kHz SCL, the TH06 may also hold the master briefly for user register and device ID transactions. At the

3. Pulses up to and including 50 ns will be suppressed.

SCL

SDA

D7

D6

D5

D0

R/W

ACK

Start Bit

Stop Bit