SM89516B datasheet(40/49 Pages) SYNCMOS

40 / 49 page

SM89516B

8-Bit Micro-controller

64KB Flash

& 1KB RAM embedded

Specifications subject to change without notice contact your sales representatives for the most recent information.

ISSFD-M087

Ver D SM89516B 08/07/2015

- 40 -

10. Watch Dog Timer

The Watch Dog Timer (WDT) is an 16-bit free-running counter that generate reset signal if the counter overflows.

The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which

causing software dead loop or runaway. The WDT function can help user software recover from abnormal software

condition. The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be

done by software periodically clearing the WDT counter. User should check WDR bit of SCONF register whenever

un-predicted reset happened. After an external reset the watchdog timer is disabled and all registers are set to

zeros.

The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit2

~ bit0 (PS[2:0]) of Watch Dog Timer Control Register (WDTC) should be set accordingly. As shown in Table 10-1.

To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter

starts to count with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when

overflows. The WDTE bit will be cleared to 0 automatically when SM89516B been reset, either hardware reset or

WDT reset.

To reset the WDT is done by setting 1 to the bit 5 (CLEAR) of WDTC. This will clear the content of the 16-bit

counter and let the counter re-start to count from the beginning.

Table 10-1: WDT time-out period

PS[2:0]

Divider

(dividing of Fosc)

Time period @ 40MHz

000

13.1ms

001

26.21ms

010

52.42ms

011

104.8ms

100

128

209.71ms

101

256

419.43ms

110

512

838.86ms

111

1024

1677.72ms

Fosc

PS[2

WDTC

PS[2:0]

WDTEN

Enable/Disable

WDT

Counter

WDTCLK

CLR

Refresh

WDT Counter

1. Power on reset

2. External reset

3. Software write “0”

WDR

Set WDR = 1

Clear

WDTF = 0

WDT time-out

reset

WDT

time-out

select

Fig. 10-1: Watchdog timer block diagram

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