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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PIC16F628-20/SS bảng dữ liệu(PDF) 79 Page - Microchip Technology |
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PIC16F628-20/SS bảng dữ liệu(HTML) 79 Page - Microchip Technology |
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79 / 160 page  © 1999 Microchip Technology Inc. Preliminary DS40300B-page 79 PIC16F62X Steps to follow when setting up an Asynchronous Transmission: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 12.1) 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, then set enable bit TXIE. 4. If 9-bit transmission is desired, then set transmit bit TX9. 5. Enable the transmission by setting bit TXEN, which will also set bit TXIF. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Load data to the TXREG register (starts trans- mission). FIGURE 12-6: ASYNCHRONOUS MASTER TRANSMISSION FIGURE 12-7: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK) TABLE 12-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on all other Resets 0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. WORD 1 Stop Bit WORD 1 Transmit Shift Reg Start Bit Bit 0 Bit 1 Bit 7/8 Write to TXREG Word 1 BRG output (shift clock) RB2/TX/CK (pin) TXIF bit (Transmit buffer reg. empty flag) TRMT bit (Transmit shift reg. empty flag) Transmit Shift Reg. Write to TXREG BRG output (shift clock) RB2/TX/CK (pin) TXIF bit (interrupt reg. flag) TRMT bit (Transmit shift reg. empty flag) Word 1 Word 2 WORD 1 WORD 2 Start Bit Stop Bit Start Bit Transmit Shift Reg. WORD 1 WORD 2 Bit 0 Bit 1 Bit 7/8 Bit 0 Note: This timing diagram shows two consecutive transmissions. |
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