PIC16C72-04SLASHSS datasheet(95/288 Pages) MICROCHIP

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DS30390E-page 95

PIC16C7X

11.5.1.2

RECEPTION

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT reg-

ister is cleared. The received address is loaded into the

SSPBUF register.

When the address byte overﬂow condition exists, then

no acknowledge (ACK) pulse is given. An overﬂow con-

dition is deﬁned as either bit BF (SSPSTAT<0>) is set

or bit SSPOV (SSPCON<6>) is set.

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-

ware. The SSPSTAT register is used to determine the

status of the byte.

FIGURE 11-25: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

A7 A6 A5 A4 A3 A2 A1

SDA

SCL

Bus Master

terminates

transfer

Bit SSPOV is set because the SSPBUF register is still full.

Cleared in software

SSPBUF register is read

ACK

Receiving Data

ACK

R/W=0

Receiving Address

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON<6>)

ACK

ACK is not sent.

Applicable Devices

72 73 73A 74 74A 76 77

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