PIC16CE623-20ESLASHSS datasheet(50/108 Pages) MICROCHIP

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PIC16CE62X

DS40182A-page 50

Preliminary

10.1

Conﬁguration Bits

The conﬁguration bits can be programmed (read as '0')

or left unprogrammed (read as '1') to select various

device conﬁgurations. These bits are mapped in

program memory location 2007h.

The user will note that address 2007h is beyond

the user program memory space. In fact, it belongs

to the special

test/conﬁguration

memory

space

(2000h – 3FFFh), which can be accessed only during

programming.

FIGURE 10-1: CONFIGURATION WORD

CP1

CP0

(2)

CP1

CP0

(2)

CP1

CP0

(2)

—

BODE

(1)

CP1

CP0

(2) PWRTE(1) WDTE F0SC1 F0SC0

CONFIG

Address

2007h

bit13

bit0

bit 13-8

CP1:CP0 Pairs: Code protection bits(2)

5-4:

Code protection for 2K program memory

= Program memory code protection off

= 0400h-07FFh code protected

= 0200h-07FFh code protected

= 0000h-07FFh code protected

Code protection for 1K program memory

= Program memory code protection off

=Program memory code protection on

= 0200h-03FFh code protected

= 0000h-03FFh code protected

Code protection for 0.5K program memory

= Program memory code protection off

= Program memory code protection of

= 0000h-01FFh code protected

bit 7:

Unimplemented: Read as '1'

bit 6:

BODEN: Brown-out Reset Enable bit (1)

1 = BOR enabled

0 = BOR disabled

bit 3:

PWRTE: Power-up Timer Enable bit (1)

1 = PWRT disabled

0 = PWRT enabled

bit 2:

WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0:

FOSC1:FOSC0: Oscillator Selection bits

= RC oscillator

= HS oscillator

= XT oscillator

= LP oscillator

Note 1:

Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure

the Power-up Timer is enabled anytime Brown-out Reset is enabled.

All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

62X.bk Page 50 Tuesday, March 10, 1998 3:40 PM

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