PIC17C752 datasheet(21/320 Pages) MICROCHIP

21 / 320 page

Preliminary

DS30264A-page 21

PIC17C75X

5.0 RESET

The PIC17CXXX differentiates between various kinds

of reset:

• Power-on Reset (POR)

• MCLR reset during normal operation

• Brown-out Reset

• WDT Reset (normal operation)

Some registers are not affected in any reset condition,

their status is unknown on POR and unchanged in any

other reset. Most other registers are forced to a “reset

state” on Power-on Reset (POR), Brown-out Reset

(BOR), on MCLR or WDT Reset and on MCLR reset

during SLEEP. A WDT Reset during SLEEP, is viewed

as the resumption of normal operation. The TO and PD

bits are set or cleared differently in different reset situ-

ations as indicated in Table 5-3. These bits are used in

software to determine the nature of the reset. See

Table 5-4 for a full description of reset states of all reg-

isters.

A simpliﬁed block diagram of the on-chip reset circuit is

shown in Figure 5-1.

Note: While the device is in a reset state, the

internal phase clock is held in the Q1 state.

Any processor mode that allows external

execution will force the RE0/ALE pin as a

low output and the RE1/OE and RE2/WR

pins as high outputs.

FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR

VDD

OSC1

WDT

Module

VDD rise

detect

OST/PWRT

On-chip

RC OSC†

WDT

Time_Out

Power_On_Reset

OST

10-bit Ripple counter

PWRT

Chip_Reset

10-bit Ripple counter

Power_Up

(Enable the PWRT timer

only during Power_Up)

(Power_Up) + (Wake_Up) (XT + LF)

(Enable the OST if it is Power_Up or Wake_Up

from SLEEP and OSC type is XT or LF)

Reset

† This RC oscillator is shared with the WDT

when not in a power-up sequence.

BOR

Module

Brown-out

Reset

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