PIC17C752 datasheet(130/320 Pages) MICROCHIP

130 / 320 page

PIC17C75X

DS30264A-page 130

Preliminary

15.1.2

SLAVE MODE

In slave mode, the data is transmitted and received as

the external clock pulses appear on SCK. When the

last bit is latched the interrupt ﬂag bit SSPIF (PIR2<7>)

is set.

While in slave mode the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

speciﬁed in the electrical speciﬁcations.

While in sleep mode, the slave can transmit/receive

data and wake the device from sleep.

15.1.3

SLAVE SELECT SYNCHRONIZATION

The SS pin allows a synchronous slave mode. The

SPI must be in slave mode with SS pin control

enabled (SSPCON1<3:0> = 04h). The pin must not

be driven low for the SS pin to function as an input.

The RA2 Data Latch must be high. When the SS pin

is low, transmission and reception are enabled and

the SDO pin is driven. When the SS pin goes high,

the SDO pin is no longer driven, even if in the

middle of a transmitted byte, and becomes a

ﬂoating output. External pull-up/ pull-down resistors

may be desirable, depending on the application.

To emulate two-wire communication, the SDO pin can

be connected to the SDI pin. When the SPI needs to

operate as a receiver the SDO pin can be conﬁgured as

an input. This disables transmissions from the SDO.

The SDI can always be left as an input (SDI function)

since it cannot create a bus conﬂict.

In Figure 15-11 the SS pin terminates the transmis-

sion/reception. The SSPIF bit is set after the last edge

of the SCK. In Figure 15-12 the SS pin causes the ﬁrst

bit of the data to be output. The SSPIF bit in set after

the last SCK edge.

Note: When the SPI is in Slave Mode with SS pin

control enabled, (SSPCON<3:0> = 0100)

the SPI module will reset if the SS pin is set

to VDD.

Note: If the SPI is used in Slave Mode with

CKE = '1', then the SS pin control must be

enabled.

FIGURE 15-9: SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb

LSb

SDO

SDI

PROCESSOR 1

SCK

SPI Master SSPM3:SSPM0 = 00xxb

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

PROCESSOR 2

SCK

SPI Slave SSPM3:SSPM0 = 010xb

Serial Clock

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