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PIC16LC62B bảng dữ liệu(PDF) 57 Page - Microchip Technology |
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PIC16LC62B bảng dữ liệu(HTML) 57 Page - Microchip Technology |
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57 / 120 page ![]() PIC16C62B/72A © 1999 Microchip Technology Inc. Preliminary DS35008B-page 57 10.2.3 RC OSCILLATOR For timing insensitive applications, the “RC” device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resis- tor (REXT) and capacitor (CEXT) values, and the operat- ing temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C compo- nents used. Figure 10-4 shows how the R/C combina- tion is connected to the PIC16CXXX. FIGURE 10-4: RC OSCILLATOR MODE 10.3 Reset The PIC16CXXX differentiates between various kinds of reset: • Power-on Reset (POR) •MCLR reset during normal operation •MCLR reset during SLEEP • WDT Reset (during normal operation) • WDT Wake-up (during SLEEP) • Brown-out Reset (BOR) Some registers are not affected in any reset condition; their status is unknown on POR and unchanged by any other reset. Most other registers are reset to a “reset state” on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR reset during SLEEP, and on Brown-out Reset (BOR). They are not affected by a WDT Wake-up from SLEEP, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared depending on the reset situation, as indicated in Table 10-4. These bits are used in software to determine the nature of the reset. See Table 10-6 for a full description of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 10-5. The PICmicro devices have a MCLR noise filter in the MCLR reset path. The filter will ignore small pulses. However, a valid MCLR pulse must meet the minimum pulse width (TmcL, Specification #30). No internal reset source (WDT, BOR, POR) willdrive the MCLR pin low. OSC2/CLKOUT Cext Rext PIC16CXX OSC1 Fosc/4 Internal clock VDD VSS Recommended values: 3 k Ω ≤ Rext ≤ 100 kΩ Cext > 20pF |
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