© 1998 Microchip Technology Inc.

Preliminary

DS21206B-page 5

93C56A/B

3.4

ERASE

The ERASE instruction forces all data bits of the spec-

ified address to the logical “1” state. This cycle begins

on the rising clock edge of the last address bit.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

ming is still in progress. DO at logical “1” indicates that

the register at the specified address has been erased

and the device is ready for another instruction.

3.5

Erase All (ERAL)

The ERAL instruction will erase the entire memory

array to the logical “1” state. The ERAL cycle is identical

to the ERASE cycle, except for the different opcode.

The ERAL cycle is completely self-timed and com-

mences at the rising clock edge of the last address bit.

Clocking of the CLK pin is not necessary after the

device has entered the ERAL cycle.

The DO pin indicates the READY/BUSY status of the

device, if CS is brought high after a minimum of 250 ns

plete.

FIGURE 3-2:

ERASE TIMING

FIGURE 3-3:

ERAL TIMING

CS

CLK

DI

DO

CHECK STATUS

1

1

•••

A0

BUSY

READY

HIGH-Z

HIGH-Z

CS

CLK

DI

DO

CHECK STATUS

10

0

1

0

X

•••

X

BUSY

READY

HIGH-Z

HIGH-Z