93C66BEP datasheet(7/12 Pages) MICROCHIP

7 / 12 page

Preliminary

DS21207B-page 7

93C66A/B

3.8

WRITE

The WRITE instruction is followed by 8 bits (93C66A)

or 16 bits (93C66B) of data which are written into the

speciﬁed address. After the last data bit is clocked into

the DI pin the self-timed auto-erase and programming

cycle begins.

The DO pin indicates the READY/BUSY status of the

device, if CS is brought high after a minimum of 250 ns

low (TCSL) and before the entire write cycle is complete.

DO at logical “0” indicates that programming is still in

progress. DO at logical “1” indicates that the register at

the speciﬁed address has been written with the data

speciﬁed and the device is ready for another instruc-

tion.

3.9

Write All (WRAL)

The WRAL instruction will write the entire memory

array with the data speciﬁed in the command. The

WRAL cycle is completely self-timed and commences

at the rising clock edge of the last data bit. Clocking of

the CLK pin is not necessary after the device has

entered the WRAL cycle. The WRAL command does

include an automatic ERAL cycle for the device. There-

fore, the WRAL instruction does not require an ERAL

instruction but the chip must be in the EWEN status.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL).

FIGURE 3-7:

WRITE TIMING

FIGURE 3-8:

WRAL TIMING

CLK

•••

BUSY

READY

HIGH-Z

Twc

TCSL

TCZ

TSV

CLK

HIGH-Z

•••

HIGH-Z

BUSY

READY

TWL

TCSL

TSV

TCZ

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