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SY100S314JC bảng dữ liệu(PDF) 1 Page - Micrel Semiconductor |
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SY100S314JC bảng dữ liệu(HTML) 1 Page - Micrel Semiconductor |
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1 / 5 page  BLOCK DIAGRAM Da Oa Oa Da Db Ob Ob Db Dc Oc Oc Dc Dd Od Od Dd De Oe Oe De VBB s Max. propagation delay of 900ps s Differential outputs s IEE min. of –60mA s Extended supply voltage option: VEE = –4.2V to –5.5V s Voltage and temperature compensation for improved noise immunity s VBB output for single-ended use s More than twice as fast as Fairchild s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages FEATURES DESCRIPTION The SY100S314 offers five differential line receivers with emitter follower outputs, designed for use in high- performance ECL systems. For single-ended operation, the VBB reference voltage is available. In the single-ended mode, the apparent input threshold of the true inputs is 30mV higher than the threshold of the complementary inputs. Common mode rejection of +1.0V is achieved through the use of active current sources. If both the true and complement inputs are at the same potential between VEE and VCC, then the complementary outputs will take on a logic HIGH state. Unlike the other members of the Synergy 300K family, the inputs on this device do not have pull- down resistors. SY100S314 QUINT DIFFERENTIAL LINE RECEIVER PIN CONFIGURATIONS Da Da Oa Oa Ob Ob Dd De Oe Dd Oe De 18 17 16 15 14 13 1 2 3 4 5 6 7 24 8 23 9 22 10 21 11 20 12 19 Top View Flatpack F24-1 Oc Oc VCCA VCC Od VCC Db VEE VBB Db Dc VEES 4 3 2 1 28 27 12 13 14 15 16 17 19 11 20 10 21 9 22 8 23 7 24 6 Top View PLCC J28-1 Od Dc 26 18 25 5 Rev.: G Amendment: /0 Issue Date: July, 1999 Pin Function Da – De Data Inputs Da – De Inverting Data Inputs Oa – Oe Data Outputs Oa – Oe Complementary Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs PIN NAMES 1 |
Số phần tương tự - SY100S314JC |
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Mô tả tương tự - SY100S314JC |
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