December 1997

7-57

MIC5891

Micrel

7

Applications Information

Serial data present at the input is transferred into the shift

register on the rising edge of the CLOCK input pulse. Additional

CLOCK pulses shift data information towards the SERIAL

DATA OUTPUT. The serial data must appear at the input prior

to the rising edge of the CLOCK input waveform.

The 8 bits present in the shift register are transferred to the

respective latches when the STROBE is high (serial-to-

parallel conversion). The latches will continue to accept new

Truth Table

Serial

Shift Register Contents

Serial

Latch Contents

Output Content

Data

Clock

Data

Strobe

Output

Input

Input

Output

Input

Enable

HH

LL

XXX

…

X

X

X

L

XXX

…

X

X

H

L

L

L …

L

L

L = Low Logic Level

H = High Logic Level

X = Irrelevant

P = Present State

R = Previous State

CLOCK

DATA IN

STROBE

OUTPUT

ENABLE

OUTN

B

D

F

E

C

G

A

H

I

Timing Conditions

data as long as the STROBE is held high. Most applications

where the latching feature is not used (STROBE tied high)

require the OUTPUT ENABLE input to be high during serial

data entry.

Outputs are active (controlled by the latch state) when the

OUTPUT ENABLE is low. All Outputs are low (disabled) when

the OUTPUT ENABLE is high. OUTPUT ENABLE does not

affect the data in the shift register or latch.