_______________Definitions of Terms

Period: The time elapsed between the first pulse’s

leading edge and the following pulse’s leading edge.

between the 1.5V level on the leading edge and the

1.5V level on the trailing edge, or vice versa.

the 20% and 80% points on the input pulse’s leading

edge.

the 80% and 20% points on the input pulse’s trailing

edge.

the 1.5V level on the input pulse’s leading edge and the

corresponding output pulse’s leading edge.

the 1.5V level on the input pulse’s trailing edge and the

corresponding output pulse’s trailing edge.

____________________Test Conditions

Ambient Temperature:

+25°C

5.0V ±0.1V

Input Pulse:

High = 3.0V ±0.1V

Low = 0.0V ±0.1V

Source Impedance:

50

Ω max

Rise and Fall Times:

3.0ns max

Pulse Width:

500ns max

Period:

1µs

Each output is loaded with a 74F04 input gate. Delay is

measured at the 1.5V level on the rising and falling

edges. The time delay due to the 74F04 is subtracted

from the measured delay.

3-in-1 Silicon Delay Line

4

_______________________________________________________________________________________

______________________________________________________________Pin Description

1

1

First Independent Input

14-PIN DIP

FUNCTION

8-PIN

DIP/SO/µMAX

NAME

16-PIN SO

2

3

Second Independent Input

4

1

IN1

IN2

3

PIN

5

Third Independent Input

4

7

Device Ground

8

6

IN3

GND

5

8

Third Delayed Output

6

10

Second Delayed Output

11

9

OUT3

OUT2

7

12

First Delayed Output

8

14

Power-Supply Input

16

13

OUT1

—

2, 4, 6, 9, 11,

13

Not Connected

2, 3, 5, 7, 10,

12, 14, 15

N.C.