Digitally Controlled Analog I/O Processor

10

MX839 PRELIMINARY INFORMATION

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4.7.2

CLOCK CONTROL Register (Hex Address $D0)

This register controls the A/D clock divide ratio:

Bits 7 to 3

Reserved for future use. These bits should be set to '0'.

DIVIDER

(Bit 2 - Bit 0)

The Xtal input clock divide ratio, which sets the A/D sample clock frequency, is defined in the

following table.

Table 5: CLOCK CONTROL Register (Hex Address $D0)

Bit 2

Bit 1

Bit 0

Function

000

Powersave

001

y1

010

y2

011

y4

100

y8

101

y16

110

y32

111

y64

Table 6: DIVIDER (Bit 2 - Bit 0)