Baseband Signal Processor

25

MX829 PRELIMINARY INFORMATION

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•COM Inc.

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7.1.4 Timing

For the following conditions unless otherwise specified:

Parameter

Notes

Min.

Typ.

Max.

Units

"CS-Enable to Clock-High"

2.0

µs

Last "Clock-High to CS-High"

4.0

µs

"CS-High to Reply Output 3-state"

2.0

µs

"CS-High" Time between transactions

2.0

µs

"Inter-Byte" Time

4.0

µs

"Clock-Cycle" time

2.0

µs

Timing Notes:

1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the peripheral MSB (bit 7) first, LSB

(bit 0) last. REPLY DATA is read from the peripheral MSB (bit 7) first, LSB (bit 0) last.

2. Data is clocked into and out of the peripheral on the rising SERIAL CLOCK edge.

3. Loaded commands are acted upon at the end of each command.

4. To allow for differing µController serial interface formats "C-BUS" compatible ICs are able to work with either polarity

SERIAL CLOCK pulses.

7

7

7

7

7

3

3

3

3

3

5

5

5

5

5

1

1

1

1

1

6

6

6

6

6

2

2

2

2

2

4

4

4

4

4

0

0

0

0

0

SERIAL CLOCK

MSB

MSB

LSB

LSB

COMMAND DATA

REPLY DATA

ADDRESS/COMMAND

BYTE

FIRST DATA BYTE

LAST DATA BYTE

LAST REPLY DATA BYTE

FIRST REPLY DATA BYTE

Logic level is not important

CS

t

CSE

t

CK

t

NXT

t

CSH

t

NXT

t

CSOFF

t

HIZ

Figure 14: "C-BUS" Timing