CMX608 datasheet(33/70 Pages) CMLMICRO

33 / 70 page

RALCWI Vocoder

CMX608/CMX618/CMX638

 2014 CML Microsystems Plc

D/608_18_38/11

Bit 2 and 3

These two bits control the period/frequency of the sync pulse output from SYNC

PERIOD

pin 25, when it is set to produce sync pulses.

Bit 3

Bit 2

Description

8kHz square wave

Pulse every 20ms

Pulse every 40ms

Pulse every 60ms

Bits 4 to 7

These bits are unused and should be cleared to '0'.

5.10.2.

8 Bit Write-Only Registers

AIG register address $05 (CMX618/CMX638 only. No function on CMX608.)

INPUT GAIN SWITCH

INPUT GAIN

This is the analogue input gain control register. Because the amplitude of speech fluctuates, it is

important to set the average speech level such that the level of distortion that results from the

occasional overdriving of the inputs is at an acceptable level. The ADC is designed not to saturate,

but will clip input signals which are too large. The ADC is a sigma-delta design with a sampling

frequency of 2.4MHz and subsequent decimation by a factor of 300.

Bits 0 to 3

These bits control the input gain stage according to the following table:

INPUT GAIN

Bit 3

Bit 2

Bit 1

Bit 0

Gain (dB)

0 (default)

1.5

3.0

4.5

6.0

7.5

9.0

10.5

12.0

13.5

15.0

16.5

18.0

19.5

21.0

22.5

Bits 4 to 6

These bits are unused and should be cleared to '0'

Bit 7

A '0' in this bit sets the microphone amplifier gain to 0dB. A '1' in this bit sets the

INPUT

microphone amplifier gain to +20dB. Using this switch will achieve a better noise

GAIN

performance than using an equivalent gain setting in bits 0-3.

SWITCH

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