IRS2168D datasheet(13/21 Pages) IRF

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IRS2168D(S)PbF

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ignition voltage) of the ballast output stage. Should this

voltage exceed the internal threshold of 1.2 V (VCSTH+), the

ignition regulation circuit controls the voltage on the VCO

pin to increase the frequency slightly (see Fig. 6). This

cycle-by-cycle feedback from the CS pin to the VCO pin

will adjust the frequency each cycle to limit the amplitude

of the current for the entire duration of ignition mode.

VCO

1.25V

Figure 6:

Ignition regulation timing diagram

When CPH exceeds 2/3*VCC (VCPHRUN+) for the second

time, the IC enters run mode and the fault counter

becomes enabled. The ignition regulation disabled in run

mode but the IC will enter fault mode after 65 (nEVENTS)

consecutive over-current faults and gate driver outputs

HO, LO and PFC will be latched low.

The output voltage of the ballast will increase during the

ignition ramp tRAMP because the frequency ramp down

from the preheat frequency to the ignition frequency and

will be constant during ignition because the ignition

regulation circuit will regulate the amplitude of the current

for the entire duration of the ignition time tIGN (Figs. 7 and

8).

During ignition mode, the PFC circuit is working in high-

gain mode and keeps the DC bus voltage regulated at a

constant level.

The high-gain mode is necessary to

prevent the DC bus from decreasing during lamp ignition

or ignition regulation. Also during ignition mode, the

SD/EOL fault is disabled.

tPH

tIGN

tRAMP

VOUT

VCPH

Figure 7:

Ballast output voltage and CPH pin during

preheat and ignition with deactivated lamp, time span

100ms

tIGN

tRAMP

VOUT

VCPH

Figure 8:

Ballast output voltage and CPH pin during

preheat and ignition with deactivated lamp, time span

50ms

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