S1003 datasheet(32/42 Pages) SII

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Giải thích chi tiết về linh kiện	MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)

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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_00

Seiko Instruments Inc.

12. Delay time (tD) vs. Temperature (Ta)

S-1003NA12

CD = 4.7 nF, VDD = 0.95 V

→ −VDET(S) + 1.0 V

−40

−25

Ta [

°C]

S-1003NA24

CD = 4.7 nF, VDD = 0.95 V

→ −VDET(S) + 1.0 V

−40

−25

Ta [

°C]

S-1003NA50

CD = 4.7 nF, VDD = 0.95 V

→ −VDET(S) + 1.0 V

−40

−25

Ta [

°C]

μs

VDD

× 90%

Input voltage

Output voltage

VIL

VSS

VIH

*1.

VIH =

−VDET(S) + 1.0 V

*2.

VIL = 0.95 V

100 k

VDD

VSS

VDD

OUT

*1.

R is unnecessary for CMOS output product.

*2.

Set to VDD or GND (MR pin non-active).

Figure 36 Test Condition for Delay Time

Figure 37 Test Circuit for Delay Time

Caution

The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.

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