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MAX521 bảng dữ liệu(PDF) 13 Page - Maxim Integrated Products |
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MAX521 bảng dữ liệu(HTML) 13 Page - Maxim Integrated Products |
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13 / 20 page ![]() Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs ______________________________________________________________________________________ 13 Setting the RST bit high clears all DAC input latches. The DAC outputs remain unchanged until a STOP con- dition is detected (Figure 10a). If a reset is issued, the following output byte is ignored. Subsequent pairs of command/output bytes overwrite the input latches (Figure 10b). All changes made during a transmission affect the MAX520/MAX521’s outputs only when the transmission ends and a STOP has been recognized. The R0, R1, and R2 bits are reserved bits that must be set to zero. I2C Compatibility The MAX520/MAX521 are fully compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain which pulls the data line low during the 9th clock pulse. Figure 11 shows a typical I2C application. Additional START Conditions It is possible to interrupt a transmission to a MAX520/ MAX521 with a new START (repeated start) condition (perhaps addressing another device), which leaves the input latches with data that has not been transferred to the output latches (Figure 12). Only the currently addressed device will recognize a STOP condition and transfer data to its output latches. If the device is left with data in its input latches, the data can be trans- ferred to the output latches the next time the device is addressed, as long as it receives at least one com- mand byte and a STOP condition. ( ) ( ) ( ) SDA 0 START CONDITION ADDRESS BYTE ACK 1 0 1 AD1 AD0 0 0 0 0010 0 (RST) (RST) STOP CONDITION COMMAND BYTE ACK ALL OUTPUTS SET TO 0 ( ) ALL INPUT LATCHES SET TO 0 ALL INPUT LATCHES SET TO 0 SDA 0 START CONDITION ADDRESS BYTE ACK 10 1 AD1 AD0 0 0 00010 0 0 STOP CONDITION COMMAND BYTE ACK "DUMMY" OUTPUT BYTE ACK (a) (b) ALL DAC OUTPUTS SET TO 0 UNLESS CHANGED BY ADDITIONAL COMMAND BYTE/OUTPUT BYTE PAIRS NOTE: X = DON'T CARE ADDITIONAL COMMAND BYTE/ OUTPUT BYTE PAIRS X X X X X X X X X X X X X X 0 OR AD2 0 OR AD2 Figure 10. Resetting DAC Outputs MAX520 SDA SCL µC SDA SCL E 2 PROM XICOR X24C04 SDA SCL AD1 AD2 AD0 QUAD DAC SDA SCL AD1 AD0 OCTAL DAC +5V MAX521 Figure 11. Typical I2C Application Circuit |
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