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MAX5253ACAP bảng dữ liệu(PDF) 4 Page - Maxim Integrated Products

tên linh kiện MAX5253ACAP
Giải thích chi tiết về linh kiện  3V, Quad, 12-Bit Voltage-Output DAC with Serial Interface
PDF  16 Pages
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nhà sản xuất  MAXIM [Maxim Integrated Products]
Trang chủ  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5253ACAP bảng dữ liệu(HTML) 4 Page - Maxim Integrated Products

  MAX5253ACAP Datasheet HTML 1Page - Maxim Integrated Products MAX5253ACAP Datasheet HTML 2Page - Maxim Integrated Products MAX5253ACAP Datasheet HTML 3Page - Maxim Integrated Products MAX5253ACAP Datasheet HTML 4Page - Maxim Integrated Products MAX5253ACAP Datasheet HTML 5Page - Maxim Integrated Products MAX5253ACAP Datasheet HTML 6Page - Maxim Integrated Products MAX5253ACAP Datasheet HTML 7Page - Maxim Integrated Products MAX5253ACAP Datasheet HTML 8Page - Maxim Integrated Products MAX5253ACAP Datasheet HTML 9Page - Maxim Integrated Products Next Button
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background image
0
-4
-8
-12
-16
-20
100
560k
1.12M
1.68M
2.24M
2.8M
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
FREQUENCY (Hz)
REFAB SWEPT 0.67Vp-p
RL = 5kΩ
CL = 100pF
-5
0
0.5
1.0
1.5
2.0
REFERENCE VOLTAGE (V)
2.5
1
0
-1
-2
-3
-4
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE
RL = 5kΩ
1000
950
900
850
800
750
700
650
600
550
500
-55 -40 -20
0
20 40
60
80
125
100
SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
CODE = FFF hex
__________________________________________Typical Operating Characteristics
(VDD = +3.3V, TA = +25°C, unless otherwise noted.)
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(VDD = +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD =1.25V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C. Output buffer connected in unity-gain configuration (Figure 9).)
CONDITIONS
tD02
SCLK Fall to DOUT Valid
Propagation Delay
tD01
SCLK Rise to DOUT Valid
Propagation Delay
ns
100
tCP
SCLK Clock Period
ns
0
tDH
DIN Hold Time
ns
40
tDS
DIN Setup Time
ns
0
tCSH
SCLK Rise to
CS Rise Hold Time
ns
40
tCSS
CS Fall to SCLK Rise Setup Time
ns
40
tCH
SCLK Pulse Width High
ns
40
tCL
SCLK Pulse Width Low
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ns
100
tCSW
CS Pulse Width High
ns
40
tCS1
CS Rise to SCLK Rise Hold Time
ns
40
tCS0
SCLK Rise to
CS Fall Delay
CL = 200pF
CL = 200pF
120
120
ns
ns



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