ICS8530-01 datasheet(9/17 Pages) IDT

9 / 17 page

ICS8530FY-01 REVISION G NOVEMBER 15, 2012

ICS8530-01 Data Sheet

LOW SKEW, 1-TO-16, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both V

SWING and VOH must meet the VPP and

CMR input requirements. Figures 2A to 2F show interface examples

for the CLK/nCLK input driven by the most common driver types. The

input interfaces suggested here are examples only. Please consult

with the vendor of the driver component to confirm the driver

termination requirements. For example in Figure 2A, the input

termination applies for IDT’s LVHSTL drivers. If you are using an

LVHSTL driver from another vendor, use their termination

recommendation.

Figure 2A. CLK/nCLK Input

Driven by an IDT LVHSTL Driver

Figure 2C. CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 2E. CLK/nCLK Input

Driven by a 3.3V HCSL Driver

Figure 2B. CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 2D. CLK/nCLK Input

Driven by a 3.3V LVDS Driver

Figure 2F. CLK/nCLK Input Driven by a 2.5V SSTL Driver

1.8V

Zo = 50

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input

125

3.3V

Zo = 50

CLK

nCLK

3.3V

LVPECL

Differential

Input

HCSL

*R3

*R4

CLK

nCLK

3.3V

Zo = 50

Differential

Input

*Optional – R3 and R4 can be 0

CLK

nCLK

Differential

Input

LVPECL

3.3V

Zo = 50

3.3V

100

LVDS

CLK

nCLK

3.3V

Receiver

Zo = 50

CLK

nCLK

Differential

Input

SSTL

2.5V

Zo = 60

2.5V

3.3V

120

ICS8530-01 bảng dữ liệu(PDF) 9 Page - Integrated Device Technology

ICS8530-01 bảng dữ liệu(HTML) 9 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

bảng dữ liệu tải về

Link URL