Quad, SPST Analog Switch

6

_______________________________________________________________________________________

tf < 20ns

tr < 20ns

50%

0V

0V

+3V

SWITCH

OUTPUT

LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES

THAT HAVE THE OPPOSITE LOGIC SENSE.

LOGIC

INPUT

SWITCH

INPUT

LOGIC

INPUT

+3V

IN_

+5V

V-

-15V

S_

GND

REPEAT TEST FOR CHANNELS 2, 3, AND 4.

(

)

+15V

V+

D_

MAX4613

Figure 2. Switching Time

Figure 1. Overvoltage Protection Using External Blocking Diodes

50%

+3V

0V

0V

LOGIC

INPUT

SWITCH

OUTPUT

SWITCH

OUTPUT

+5V

+15V

V+

S_

V-

-15V

0V

GND

LOGIC

INPUT

0V

IN_

S_

D_

D_

MAX4613

Figure 3. Break-Before-Make Test Circuit

______________________________________________Timing Diagrams/Test Circuits

supply; connect V- to GND when operating with a sin-

gle supply. Also, all device types can operate with

be connected to +5V to be TTL compatible, or to V+ for

CMOS-logic level inputs. The

Typical Operating

Characteristics graphs show typical on-resistance with

±20V, ±15V, ±10V, and ±5V supplies. (Switching times

increase by a factor of two or more for operation at ±5V.)

Overvoltage Protection

Proper power-supply sequencing is recommended

for all CMOS devices. Do not exceed the absolute

maximum ratings because stresses beyond the list-

ed ratings may cause permanent damage to the

devices. Always sequence V+ on first, followed by

is not possible, add two small, external signal

diodes in series with supply pins for overvoltage

protection (Figure 1). Adding diodes reduces the

analog signal range to 1V below V+ and 1V above

V-, but low switch resistance and low leakage char-

acteristics are unaffected. Device operation is

unchanged, and the difference between V+ and V-

should not exceed +44V.

V+

D

V-

S