ICS570

MULTIPLIER AND ZERO DELAY BUFFER

ZDB AND MULTIPLIER

IDT™ / ICS™ MULTIPLIER AND ZERO DELAY BUFFER

4

ICS570

REV K 073007

Using CLK as the feedback will always result in synchronized rising edges between ICLK and CLK. However, the

CLK/2 could be a falling edge compared with ICLK. IDT recommends using CLK/2 feedback whenever possible.

This will synchronize the rising edges of all three clocks.

Clock Period Jitter Tables (ICS570A)

All jitter values are considered typical measured at 25

° C with 27Ωtermination resistor and 15 pF loads on both CLK

and CLK/2. The feedback is from CLK/2 to FBIN. Note that if an output is unused, it should be left unconnected to

improve output jitter on the active output clocks.

Absolute and One Sigma Jitter (ps)

Absolute and One Sigma Jitter (ps)

Absolute and One Sigma Jitter (ps)

CLK = 50M

CLK/2 = 25M

S

S

CLKIN

Multiplier

P to P

1 sigma

Multiplier

P to P

1 sigma

0

M

8.333

6x

±115

80

3x

±65

20

0

1

6.25

8x

±115

80

4x

±60

20

M

0

3.125

16x

±120

80

8x

±55

20

M

M

4.167

12x

±120

90

6x

±60

20

M

1

2.5

20x

±120

80

10x

±60

20

1

0

25

2x

±120

70

1x

±55

20

1

M

1.5625

32x

±120

80

16x

±50

20

1

1

12.5

4x

±120

80

2x

±55

20

CLK = 100M

CLK/2 = 50M

S

S

CLKIN

Multiplier

P to P

1 sigma

Multiplier

P to P

1 sigma

0

M

16.667

6x

±135

100

3x

±55

20

0

1

12.5

8x

±140

100

4x

±50

20

M

0

6.25

16x

±140

110

8x

±55

20

M

M

8.333

12x

±140

110

6x

±55

20

M

1

5

20x

±135

100

10x

±50

20

1

0

50

2x

±120

90

1x

±50

20

1

M

3.125

32x

±135

100

16x

±55

20

1

1

25

4x

±130

90

2x

±65

20

CLK = 150M

CLK/2 = 75M

S

S

CLKIN

Multiplier

P to P

1 sigma

Multiplier

P to P

1 sigma

0

M

25

6x

±160

120

3x

±55

20

0

1

18.375

8x

±165

120

4x

±55

20

M

0

9.375

16x

±170

120

8x

±50

20

M

M

12.5

12x

±160

120

6x

±55

20

M

1

7.5

20x

±160

120

10x

±55

20