6-OUTPUT 3.3V PCIE GEN 1-2-3 CLOCK GENERATOR

2

REVISION B 07/17/15

9FGL06 DATASHEET

Pin Configuration

SMBus Address Selection Table

Power Connections

40 39 38 37 36 35 34 33 32 31

vSS_EN_tri 130 vOE3#

X1_25 229 DIF3#

X2 328 DIF3

VDDXTAL3.3 427 VDDIO

VDDREF3.3 526 VDDA3.3

vSADR/REF3.3 625 NC

NC 724 vOE2#

GNDDIG 823 DIF2#

SCLK_3.3 922 DIF2

SDATA_3.3 10

21 vOE1#

11 12 13 14 15 16 17 18 19 20

v

prefix indicates internal 120KOhm pull down resistor

^

prefix indicates internal 120KOhm pull up resistor

9FGL06xx

epad is GND

40-pin VFQFPN, 5x5 mm, 0.4mm pitch

SADR

Address

0

1101000

1

1101010

State of SADR on first application

of CKPWRGD_PD#

+

Read/Write Bit

x

x

True O/P

Comp. O/P

0X

X

1

1

0

Running

Running

Running

11

1

Running

10

X

1. The output state is set by B11[1:0] (Low/Low default)

3. Input polarities defined at default values for 9FGL0641/0651.

4. See SMBus description for Byte 3, bit 4

REF

CKPWRGD_PD#

SMBus

OE bit

2. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when

CKPWRG_PD# is low, REF is disabled unless Byte3[5]=1, in which case REF is

running.

DIFx

OEx# Pin

Pin Number

VDD

VDDIO

GND

441

XTAL OSC

5

41

REF Power

11

8

Digital (dirty)

Power

12,17,27,32,39

41

DIF outputs

26

41

PLL Analog

Description