CS5124 datasheet(6/11 Pages) ONSEMI

6 / 11 page

CS5124

http://onsemi.com

VCC UVLO COMP

VREF = 5.0 V

OSC

DIS

RAMP

V5REF

VREFOK

GND

ISENSE

VFB

GATE

VCC

UVLO

BIAS

V5REF

VCC

LINE AMP

2.0 V

V 1.91 V/1.83 V

2.62 V/2.45 V

TSHUT

7.7 V/7.275 V

490 mV

10 mA

INE UVLO COMP

REMOTE

(SLEEP) COMP

150°C/125°C

SS AMP

BLANKING

1000 W

DRIVER

BLANK

ICOMP

2ND

SET DOMAIN

RESET DOMAIN

170 mV/ms

VCC

−

4500 W

1.32 V

2.90 V

SS COMP

Soft−Start LATCH

PWM COMP

VFB COMP

60 mV

ENABLE

275 mV

1/10

2.9 R

Figure 2. Block Diagram

THEORY OF OPERATION

Powering the IC

VCC can be powered directly from a regulated supply and

requires 500

mA of startup current. The CS5124 includes a

line bias pin (BIAS) that can be used to control a series pass

transistor for operation over a wide input voltage. The BIAS

pin will control the gate voltage of an N−channel MOSFET

placed between VIN and VCC to regulate VCC at 8.0 V.

VCC and UVLO Pins

The UVLO pin has three different modes; low power

shutdown, Line UVLO, and normal operation. To illustrate

how the UVLO pin works; assume that VIN, as shown in the

application schematic, is ramped up starting at 0 V with the

UVLO pin open. The SS and ISENSE pins also start at 0 V.

While the UVLO is below 1.8 V, the IC will remain in a low

current sleep mode and the BIAS pin of the CS5124 is

internally clamped to a maximum of 15 V. When the voltage

on the UVLO pin rises to between 1.8 V and 2.6 V the

reference for the VCC UVLO is enabled and VCC is

regulated to 8.0 V by the BIAS pin, but the IC remains in a

UVLO state and the output driver does not switch. When the

UVLO pin exceeds 2.6 V and the VCC pin exceeds 7.7 V, the

GATE pin is released from a low state and can begin

switching based on the comparison of the ISENSE and VFB

pins. The Soft−Start capacitor begins charging from 0 V at

mA. As the capacitor charges, a buffered version of the

capacitor voltage appears on the VFB pin and the VFB

voltage begins to rise. As VFB rises the duty cycle increases

until the supply comes into regulation.

Soft−Start

Soft−Start is accomplished by clamping the VFB pin 1.32 V

below the SS pin during normal start up and during restart

after a fault condition. When the CS5124 starts, the

Soft−Start capacitor is charged from a 10

mA source from 0

V to 4.9 V. The VFB pin follows the Soft−Start pin offset

by −1.32 V until the supply comes into regulation or until

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