RFAC3612 datasheet(4/15 Pages) RFMD

4 / 15 page

RF Micro Devices Inc.

7628 Thorndike Road, Greensboro, NC 27409-9421

DS140530

For sales or technical support, contact RFMD at +1.336.678.5570 or customerservice@rfmd.com.

The information in this publication is believed to be accurate. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents or other rights of

third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended

application circuitry and specifications at any time without prior notice.

4 of 15

RFAC3612

Parameter

Specification

Unit

Condition

Min

Typ

Max

States 0 to 63

-65

dBm

PFWD = 33dBm, f0 = 1910MHz

Series Configuration, Nonlinear

Parameters

– Cont.

Input IP2

– States 0 to 63 (IP2SERIES)

Cell Low

115

dBm

See IP2 / IP3 test conditions table below

Cell High

132

dBm

IMT Low

129

dBm

IMT High

130

dBm

See IP2 / IP3 test conditions table below

GPS Test 1

140

dBm

GPS Test 2

140

dBm

Band 8 (800MHz to 960MHz)

126

dBm

Tone 1 at 20dBm

Bands 2, 4, 7, 11 (1428MHz to 2690MHz)

128

dBm

Tone 2 at -15dBm

Input IP3 (States 0 to 63 (IP3SERIES)

Cell (B5)

dBm

See IP2 / IP3 test conditions table below

IMT (B1)

dBm

– LTE Test 1

dBm

– LTE Test 2

dBm

Band 8 (800MHz to 960MHz)

dBm

Tone 1 at 20dBm

Bands 2, 4, 7, 11 (1428MHz to 2690MHz)

dBm

Tone 2 at -15dBm

RF1 to RF2 Spurious (all States

No RF

-120

dBm

400MHz to 2700MHz

915MHz at 35dBm

-112

dBm

925MHz to 960MHz

1910MHz at 33dBm

-113

dBm

1930MHz to 1990MHz

General Electrical Specifications

Power-up Time (tPOWER-UP)

µs

Time from VDD within specification to all specifications is met.

Switching Time-Small Signal (tSWITCH, SS)

µs

Time from programming (falling edge of SCLK of the 16

th bit) to

90% of capacitance change achieved

Stitching Time

– Large Signal (tSWITCH, LS)

µs

Time from programming (falling edge of SCLK of the 16

th bit) to

power handling and linearity specifications are met

3-Wire Interface Timing

Characteristics

Serial Clock Frequency (fSCLK = 1/tSCLK)

MHz

Clock High and Low Time (tSCLKHIGH,

tSCLKLOW)

0.45 x

tSCLK

0.55 x

tSCLK

Falling Edge of CS to Rising Edge of SCLK

Set-up Time, Start of Telegram (tCS_SCLK)

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