NJG1104KB2

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nTERMINAL INFORMATION

Pin

Function

Description

1

SOURCE

This terminal is internally connected to FET’s source of LNA. Please connect self-

bias resistor (R1) and bypass capacitor (C3) through source inductor (L5). NF and

IIP3 are tunable by C3 and L5.

2, 4

GND

Ground (0V) terminal. Ground plane should be placed as close to the ground

terminals. .

3

RFout

RF output and drain voltage supplies terminal. External matching circuit is

required.

5

6

RFin

RF input terminal. External matching circuit and DC blocking capacitor are required.