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RF2052

DS140110

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.

lowed by a ‘1’ (to indicate a read operation), followed by a seven bit address. A 1.5 bit delay is introduced before the sixteen bit

data word representing the register content is presented to the receiver.

Note that since the serial bus does not require the presence of the crystal clock, it is necessary to insert an additional rising

clock edge before the ENX line is set low to ensure the address is read correctly.

Hardware Control

Three hardware control pins are provided: ENBL, MODE, and RESETB.

ENBL Pin

The ENBL pin has two functions: to enable the analog circuits in the chip and to trigger the VCO band selection as described in

the VCO section on page 10.

As outlined in the VCO section the chip has a built-in automatic VCO band selection to tune the selected VCO to the desired fre-

quency. The band selection is initiated when the ENBL pin is taken high. Every time the frequency of the synthesizer is re-pro-

grammed, the ENBL has to be inserted high to initiate the automatic VCO band selection (VCO coarse tune).

RESETB Pin

The RESETB pin is a hardware reset control that will reset all digital circuits to their start-up state when asserted low. The

device includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to

the positive supply.

MODE Pin

The MODE pin controls which PLL programming register bank is active.

For normal operation of the RF2052 the MODE pin should be set high to select the default PLL2 programming registers. It is

possible to set the FULLD bit in the CFG1 register high. This allows the MODE pin to select either PLL1 register bank

(MODE=low) or PLL2 register bank (MODE=high). This may be useful for some applications where two LO frequencies can be

programmed into the registers then the MODE pin used to toggle between them. The ENBL pin will also need to be cycled to re-

lock the synthesizer for each frequency.

ENBL Pin

REFSTBY Bit

XO and Bias Block

Analogue Block

Digital Block

Low

0

Off

Off

On

Low

1

On

Off

On

High

0

OnOnOn

High

1

OnOnOn

Parameter

Description

Time

t1

MODE setup time

>5ns

t2

MODE hold time

>5ns

ENBL

MODE

t1

t2