UPD78P4908 datasheet(39/64 Pages) NEC

39 / 64 page

µPD78P4908

Data Sheet U11681EJ2V0DS00

DATA RETENTION CHARACTERISTICS (TA = –40

°C to +85 °C)

Notes 1. Valid when input voltages to the pins described in Note 2 satisfy VIL or VIH in the above table.

2. RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3,

P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3, and

P107/SO3 pins

AC TIMING TEST POINTS

Parameter

Data retention voltage

Data retention current

VDD rise time

VDD fall time

VDD hold time

(to STOP mode setting)

STOP clear signal input time

Oscillation settling time

Input low voltage

Input high voltage

Conditions

STOP mode

VDDDR = 2.5 V, AVREF =

0 VNote 1

VDDDR = 4.0 to 5.5 V,

AVREF1 = 0 VNote 1

Crystal resonator

Ceramic resonator

Specific pinsNote 2

MIN.

2.5

200

0.9 VDDDR

TYP.

MAX.

5.5

0.1 VDDDR

VDDDR

Unit

µA

µs

Symbol

VDDDR

IDDDR

tRVD

tFVD

tHVD

tDREL

tWAIT

VIL

VIH

0.8 VDD or 2.2 V

0.8 V

0.8 VDD or 2.2 V

0.8 V

Test points

VDD – 1 V

0.45 V

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