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UPD78P324LP bảng dữ liệu(PDF) 52 Page - NEC |
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UPD78P324LP bảng dữ liệu(HTML) 52 Page - NEC |
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52 / 80 page ![]() µPD78P324, 78P324(A) 52 (4) µPD78P324(A2) Electrical Specifications (3/9) Oscillator Characteristics (TA = 40 to +125 °C, VDD = +5 V ±10 %, VSS = 0 V) Oscillator Ceramic oscillator or crystal oscillator External clock Recommended Circuit Parameter Oscillation frequency (fXX) X1 input frequency (fX) X1 input rise time, fall time (tXR, tXF) X1 input high-/low-level width (tWXH, tWXL) MIN. MAX. Unit 8 12.5 MHz 8 12.5 MHz 020 ns 46 100 ns Caution When using the system clock oscillation circuit, wire the part encircled in the dotted line in the following manner to avoid the influence of the wiring capacity, etc. • Make the wiring as short as possible. • Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating currents run. • Make sure that the grounding point of the oscillation circuit capacitor always has the same electrical potential as VSS. Avoid grounding with a grand pattern in which very high currents run. • Do not fetch signals from the oscillation circuit. X2 X1 VSS C2 C1 X2 X1 X2 X1 HCMOS inverter HCMOS inverter or No connection required |
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