LMU112PC50 datasheet(1/6 Pages) LODEV

tên linh kiện	LMU112PC50

Giải thích chi tiết về linh kiện	12 x 12-bit Parallel Multiplier

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nhà sản xuất	LODEV [LOGIC Devices Incorporated]

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DEVICES INCORPORATED

LMU112

12 x 12-bit Parallel Multiplier

Multipliers

08/16/2000–LDS.112-K

1

u

u 25 ns Worst-Case Multiply Time

u

u Low Power CMOS Technology

u

u Replaces Fairchild MPY112K

u

u Two’s Complement or Unsigned

Operands

u

u Three-State Outputs

u

u Package Styles Available:

• 48-pin PDIP

• 52-pin PLCC, J-Lead

FEATURES

DESCRIPTION

LMU112

12 x 12-bit Parallel Multiplier

DEVICES INCORPORATED

The LMU112 is a high-speed, low

power 12-bit parallel multiplier built

using advanced CMOS technology.

The LMU112 is pin and functionally

compatible with Fairchilds’s MPY112K.

The A and B input operands are

loaded into their respective registers

on the rising edge of the separate

clock inputs (CLK A and CLK B).

Two’s complement or unsigned

magnitude operands are accommo-

dated via the operand control bit (TC)

LMU112 BLOCK DIAGRAM

A REGISTER

CLK A

CLK B

12

24

OE

B11-0

A11-0

R23-8

TC

FORMAT ADJUST

16

B REGISTER

RESULT REGISTER

16

which is loaded along with the B

operands. The operands are specified

to be in two’s complement format

when TC is asserted and unsigned

magnitude when TC is deasserted.

Mixed mode operation is not allowed.

For two’s complement operands, the

17 most significant bits at the output

of the asynchronous multiplier array

are shifted one bit position to the left.

This is done to discard the redundant

copy of the sign-bit, which is in the

most significant bit position, and

extend the bit precision by one bit.

The result is then truncated to the 16

MSB’s and loaded into the output

register on the rising edge of CLK B.

The contents of the output register are

made available via three-state buffers

by asserting OE. When OE is de-

asserted, the outputs (R23-8) are in the

high impedance state.

Số phần tương tự - LMU112PC50

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