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LF2242 bảng dữ liệu(PDF) 2 Page - LOGIC Devices Incorporated |
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LF2242 bảng dữ liệu(HTML) 2 Page - LOGIC Devices Incorporated |
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2 / 8 page  DEVICES INCORPORATED LF2242 12/16-bit Half-Band Interpolating/ Decimating Digital Filter Video Imaging Products 2 08/16/2000–LDS.2242-K Controls INT — Interpolation Control When INT is LOW and DEC is HIGH (Table 1), the device internally forces every other incoming data sample to zero. This effectively halves the input data rate and the output amplitude. DEC — Decimation Control When DEC is LOW and INT is HIGH (Table 1), the output register is strobed on every other rising edge of CLK (driven at halftheclockrate),decimatingtheoutput data stream. FIGURE 1. FREQUENCY RESPONSE OF FILTER SIGNAL DEFINITIONS Power VCC and GND +5 V power supply. All pins must be connected. Clock CLK — Master Clock The rising edge of CLK strobes all regis- ters. All timing specifications are refer- enced to the rising edge of CLK. SYNC — Synchronization Control Incoming data is synchronized by hold- ing SYNC HIGH on CLKN, and then by bringing SYNC LOW on CLKN+1 with the first word of input data. SYNC is held LOW until resynchronization is desired, or it can be toggled at half the clock rate. For interpolation (INT = LOW), input data should be presented at the first ris- ing edge of CLK for which SYNC is LOW and then at every alternate rising edge of CLK thereafter. SYNC is inactive if DEC and INT are equal (pass-through mode). Inputs SI11–0 — Data Input 12-bit two’s complement data input port. Data is latched into the register on the rising edge of CLK. The LSB is SI0 (Figure 2). Outputs SO15-0 Data Output The current 16-bit result is available on the SO15-0 outputs. The LF2242’s limiter ensures that a valid full-scale (7FFF positive or 8000 negative) output will be generated in the event of an internal overflow. The LSB is SO0 (Figure 2). 0 0.1 ƒ S 0.2 ƒ S 0.3 ƒ S 0.4 ƒ S 0.5 ƒ S FREQUENCY (NORMALIZED) 0 –10 –20 –30 –40 –50 –60 –70 –80 INT DEC MODE 0 0 Pass-through* 0 1 Interpolate 1 0 Decimate 1 1 Pass-through* *Input and output registers run at full clock rate TABLE 1. MODE SELECTION |
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