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M5-128/104-10VC bảng dữ liệu(PDF) 3 Page - Lattice Semiconductor

tên linh kiện M5-128/104-10VC
Giải thích chi tiết về linh kiện  Fifth Generation MACH Architecture
PDF  47 Pages
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M5-128/104-10VC bảng dữ liệu(HTML) 3 Page - Lattice Semiconductor

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MACH 5 Family
3
Note:
1. C = Commercial grade, I = Industrial grade
2. /1 version recommended for new designs
3. Preliminary specificatons
With Lattice’s unique hierarchical architecture, the MACH 5 family provides densities up to 512
macrocells to support full system logic integration. Extensive routing resources ensure pinout
retention as well as high utilization. It is ideal for PAL® block device integration and a wide range
of other applications including high-speed computing, low-power applications, communications,
and embedded control. At each macrocell density point, Lattice offers several I/O and package
options to meet a wide range of design needs (Table 3).
Note:
1. The I/O options indicated with a “*” are obsolete, please contact factory for more information.
Table 2. MACH 5 Speed Grades
Device
Speed Grade1
-5
-6
-7
-10
-12
-15
-20
M5-1282
C
C, I
C, I
C, I
I
M5-128/1
C
C, I
C, I
C, I
C, I
I
M5LV-128
C
C,I
C, I
C, I
I
M5-192/1
C
C, I
C, I
C, I
C, I
I
M5-2562
C
C, I
C, I
C, I
I
M5-256/1
C
C, I
C, I
C, I
C, I
I
M5LV-256
C
C, I
C, I
C, I
I
M5-320
C
C, I
C, I
C, I
C, I
I
M5LV-320
C
C, I
C, I
C, I
C, I
I
M5-384
C3
C, I3
C, I
C, I
C, I
I
M5LV-384
C3
C, I3
C, I
C, I
C, I
I
M5-512
C3
C, I3
C, I
C, I
C, I
I
M5LV-512
C3
C, I3
C, I
C, I
C, I
I
Table 3. MACH 5 Package and I/O Options 1
M5-128/1
M5LV-128
M5-192/1
M5-256/1
M5LV-256
M5-320
M5LV-320
M5-384
M5LV-384
M5-512
M5LV-512
Supply Voltage
5
3.3
5
5
3.3
5
3.3
5
3.3
5
3.3
100-pin TQFP
68
68, 74
68
68
68*, 74
100-pin PQFP
68
68*
68*
68*
68
144-pin TQFP
104
104
144-pin PQFP
104
104*
104*
104*
104*
160-pin PQFP
120
120
120
120
120
120*
120
120*
120
120*
120
208-pin PQFP
160
160
160
160
160
160
160
160
240-pin PQFP
184*
184*
184*
184*
184*
184*
256-ball BGA
192
192*
192*
192*
192*
192*
352-ball BGA
256
256



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